Integrated circuits (ICs) are sophisticated semiconductor components that provide processing, memory, and storage capabilities to modern electronic devices. Advances in IC fabrication have enabled a wide range of devices from wearable devices to surgical robots. ICs comprise a number of layers of intricate sub-micrometer scale structures that implement rudimentary logic and memory cells. Fabrication of ICs comprise hundreds of process steps, such as implantation, deposition, lithography, etching, polishing, and packaging, that transform a bare semiconductor wafers into ICs. Upon fabrication, ICs are tested to check if their functional performance meets target specifications. The ratio of the number of ICs that meet target specifications to the total number of fabricated ICs is known as production yield. Since yield has a direct impact on the cost of an IC, maximizing yield is an important activity in semiconductor fabrication.
Maximizing yield, however, is a challenging task because of the exhaustive number and complexity of steps involved in IC fabrication. To facilitate the task, wafer inspection and metrology systems are employed to inspect for abnormalities after each significant process step. For example, a wafer inspection system may be used for detecting defects; a wafer review system may be used for resolving and identifying defects; a wafer metrology system may be used for measuring the properties of one or more films on a wafer; and a wafer shape system may be used for measuring the shape of a wafer. Abnormalities or defects detected by wafer inspection and metrology systems are monitored closely. When the abnormalities or defects become intolerable, process steps are adjusted in an effort to bring them back to tolerable levels.
Advances in semiconductor fabrication such as node scaling, 3D transistors, 450 mm wafer size, and the use of new materials have brought upon increased challenges to wafer inspection and metrology systems. Node scaling refers to the trend of decreasing size of components inside ICs. Node scaling and increasing wafer size have allowed ICs to improve their performance (increased speed, reduced power, increased memory capacity, increased memory bandwidth) while simultaneously reducing their cost. However, wafer inspection systems have not been able to effectively meet the challenges imposed by advances in semiconductor fabrication. For example, while the smallest IC structures shrank from 130 nm to 14 nm (over 9× reduction) over the last decade, defect sensitivity of optical wafer inspection systems improved at a substantially slower rate from 50 nm to 20 nm (2.5× reduction) in the same time period. Since the size of yield affecting defects decreases at the same rate as node scaling, the slower rate of improvement in defect sensitivity has resulted in a negative impact on yield.
Wafer inspection systems capture a large amount of data to inspect a wafer. For instance, in a typical wafer inspection system, a micrometer scale laser beam is scanned over a wafer as large as few hundred millimeters. Light scattered from each point on the wafer is captured. Wafer size can be as large as 450 mm, and the number of points can be over a billion. Typical wafer inspection systems exhibit defect sensitivity of about 20 nm. This means that a 20 nm size spherical particle made out of silica or polystyrene latex can be reliably detected. A 20 nm particle has a surface area that is over 100 trillion times smaller than the surface area of a 450 mm wafer. Accordingly, detecting such small defects reliably requires high-performance computing systems that operate on a large quantity of data.
A traditional wafer inspection system employs a high performance computer that is collocated with an inspection module. The computer has finite processing, memory, and storage capabilities. The computer executes a software application to process the above mentioned large quantity of data. Accordingly, computing is centralized in a traditional wafer inspection system. Such centralization increases the risk of a single point of failure. That is, any malfunction in software, processor, memory, or storage could make the wafer inspection system non-functional. Therefore, computing infrastructure in traditional wafer inspection systems is not reliable. Further, the computing infrastructure in a traditional inspection system is not scalable. That is, the processing, memory, and storage capabilities cannot be arbitrarily expanded in a traditional wafer inspection system. Furthermore, the computing infrastructure is not upgradable or downgradable on demand. That is, the processing, memory, and storage capabilities cannot be readily reconfigured in a traditional wafer inspection system. The lack of reliability, scalability, and upgradability of computing infrastructure in traditional wafer inspection systems restricts traditional wafer inspection systems from using sophisticated data processing techniques.
Although traditional wafer inspection and metrology systems detect defects and abnormalities, they do not have the capability to classify yield affecting defects from other harmless defects. On the one hand, this may lead to negligence of root-cause analysis for yield affecting defects. On the other hand, this may also lead to needless root-cause analysis for harmless defects. Further, the information generated by traditional wafer inspection techniques are restricted to data obtained from a wafer under inspection. As a result, analytical trends about yield-affecting wafer characteristics are unavailable.
Maximizing yield involves using information provided by wafer inspection and metrology systems to identify and correct the root cause of abnormalities or defects that are responsible for rendering an IC non-functional. However, doing so is a formidable challenge because of the exhaustive range of failure modes in IC fabrication. In other words, the challenge is to identify abnormalities or defects responsible for the failure of an IC from hundreds of process steps. Traditional wafer inspection techniques do not have the capability to analytically identify the root cause of IC failures.
Traditional wafer inspection suffers from a number of problems, including: a) lack of a reliable computing infrastructure; b) lack of a scalable computing infrastructure; c) lack of an upgradable computing infrastructure; d) inability to classify yield affecting defects/abnormalities from harmless defects/abnormalities; e) inability to generate trends about yield-affecting defects/abnormalities; and f) inability to identify root cause of yield affecting defects/abnormalities.
Accordingly, there is a need for an improved wafer inspection system and a method that has a reliable, scalable, and upgradable computing infrastructure; has the ability to classify yield affecting defects/abnormalities from harmless defects/abnormalities; has the ability to generate trends about yield-affecting defects/abnormalities; and has the ability to identify root cause of yield affecting defects/abnormalities.